Conductive anodic filament (CAF) failure has become a critical reliability concern in modern printed wiring boards (PWBs). As designs push toward finer pitch, higher layer counts, and higher operating voltages, the risk of CAF increases. CAF refers to the growth of a conductive copper filament through the glass/epoxy dielectric under bias and humidity, bridging adjacent conductors. These failures typically occur below the surface of the laminate, making them difficult to detect until electrical breakdown occurs.

 

Fig.1 – Plated copper is deep in the dielectric space between holes in the laminate.

CAF formation is often associated with copper plating extending beyond the plated through hole wall into adjacent resin-rich regions. Once copper is introduced into these dielectric pathways, bias and moisture accelerate ion migration. The resulting copper grows along glass/resin interfaces, creating hidden conductive bridges deep inside the laminate stack.

 

Fig. 2 – Failures were caused by CAF between +12V and GND at a connector.

CAF is particularly insidious when it forms between high and low potential conductors, such as +12 V and ground nets. Even small leakage currents can result in intermittent failures, system resets, or complete short circuits.

 

Fig. 3 – Resin starvation in glass bundles can cause CAF failure.

Areas where resin coverage is poor around glass bundles provide prime initiation sites. Resin starvation leaves microvoids and channels at the fiber-resin interface. These gaps act as capillaries for moisture and ionic species, establishing a pathway for CAF growth. Process controls during lamination—such as ensuring proper resin flow and glass fabric wetting are therefore crucial to prevention.

 

 

Fig. 4 – Crazing and measling of laminate can support CAF failure.

Crazing and measling are microcrack and void patterns associated with glass bundle movement or thermal-mechanical stresses. These features effectively increase the available surface area and pathways for CAF propagation. A laminate that visually shows measling may already harbor hidden weaknesses that accelerate conductive filament growth under bias and humidity stress testing.

 

Fig. 5 – Dark field optical images can be useful for examining fiber delamination in PWB sections.

Optical microscopy, particularly in dark field mode, highlights fiber pullout, voiding, and microcracking within cross-sections. These imaging techniques provide valuable insight into resin-glass integrity and delamination. Proper sectioning and imaging remain vital diagnostic steps in CAF investigations.

Conclusion

CAF originates inside the laminate microstructure, where resin-glass interfaces and plating intrusions provide pathways for copper migration. Once established, these conductive filaments undermine reliability and are difficult to detect by conventional inspection. Effective CAF prevention requires careful control of laminate fabrication, resin distribution, and design spacing rules, coupled with targeted failure analysis methods when issues arise.

 

Weibull analysis is a powerful statistical tool commonly used in electronics reliability engineering to model failure behavior over time. Its flexibility in handling different failure modes—early life, random, or wear-out—makes it especially valuable in the complex, multi-mechanism failure environments typical of electronic components and assemblies.

These are key use cases for Weibull analysis in electronics reliability:

 

 

 

1.

Failure Mode Characterization

 

 

 

• Purpose: Determine whether a failure mode is infant mortality, random, or wear-out.

• Example: Analyzing time-to-failure data for a batch of surface mount capacitors under thermal cycling to distinguish between early cracking (β < 1), random failures (β ≈ 1), or fatigue wear-out (β > 1).

 

 

 

 

2.

Life Prediction / Time-to-Failure Estimation

 

 

• Purpose: Estimate the median life or characteristic life (η) of a device under use or test conditions.

• Example: Predicting BGA solder joint fatigue life under power cycling stress based on accelerated test data.

 

 

 

 

3.

Accelerated Life Testing (ALT) and Extrapolation

 

 

• Purpose: Use high-stress data (e.g., temperature, humidity, voltage) to model life at normal use conditions using acceleration models (e.g., Arrhenius, Coffin-Manson, Norris-Landzberg).

• Example: Subjecting PCBs to elevated temperature and humidity to simulate dendritic growth or corrosion, then applying Weibull + acceleration models to estimate field failure rates.

 

 

 

 

4.

Comparative Reliability of Designs, Materials, or Processes

 

 

• Purpose: Compare different design or material variants to determine which one offers longer life or fewer failures.

• Example: Comparing ENIG vs. ENEPIG surface finishes by running temperature cycle tests and plotting separate Weibull curves to assess which has higher characteristic life.

 

 

 

 

5.

Failure Rate Estimation (λ) and MTBF Calculations

 

 

• Purpose: Derive Mean Time Between Failures (MTBF) or failure rate, especially in systems with a constant failure rate (β ≈ 1).

• Example: Estimating MTBF for a power supply module operating in a data center, where failures are largely random due to overstress or component defects.

 

 

 

 

6.

Warranty and Risk Forecasting

 

 

• Purpose: Predict percentage of devices that will fail before a specific time to define warranty coverage.

• Example: Forecasting the probability that LED driver ICs will fail within a 5-year service window in a commercial lighting application.

 

 

 

 

7.

Root Cause Correlation

 

 

• Purpose: Identify underlying mechanisms by examining how β (Weibull slope) changes with design, processing, or test variables.

• Example: If β increases significantly after a design change, it may indicate better control over early life defects.

 

 

 

 

8.

Field Return Analysis

 

 

• Purpose: Apply Weibull analysis to returned units from the field to distinguish between systemic failures and random defects.

• Example: Analysis of failed MLCCs from automotive ECUs to determine if failures are consistent with mechanical flex cracking (brittle failure, high β) or ESD-related dielectric breakdown (random).

 

 

 

 

9.

Burn-In Screening Optimization

 

 

• Purpose: Use early life Weibull data (β < 1) to justify burn-in screening duration and effectiveness.

• Example: Determining if 24-hour power-on burn-in is sufficient to weed out early IC failures caused by latent defects.

 

 

 

 

 

10.

Reliability Growth Tracking

 

 

• Purpose: Show how process improvements (e.g., cleaning, soldering controls, layout changes) shift the Weibull distribution toward higher reliability.

• Example: Tracking Weibull parameters of conformal-coated PCBs before and after changing flux chemistry or cleaning method.

 

 

We can write equations and make calculations based on atomic weight & density of pure elements to determine what volume change (%) occurs when for example Au + 4Sn >>> AuSn4 and using intermetallic densities from published sources as shown in Fig. A.

Fig. A – Volume change during formation of solder intermetallic compounds.

Since volume changes during IMC formation, we can expect void formation and interfacial cracking at the IMC/matrix interface as most of these systems show contractions in volume. This may be a contributing factor to thermal fatigue damage found in solder joints on printed circuit board assemblies.

The melting temperature of these intermetallic compounds are shown in Fig. B.  Most of these melting temperatures are greater than peak reflow temperature, so the IMCs exist as solid particles in molten solder until the system cools below the solidus temperature.

Fig. B – Melting temperature of intermetallic compounds.

 

 

 

SLI_Insight: How I Built a Local Expert Assistant for Electronics Failure Analysis

By Ed Hare

Consultant in Electronic Materials, Reliability, and Failure Analysis

⸻

For more than 27 years, I’ve investigated and solved quality and reliability issues across the electronics industry. In that time, I’ve seen the same problems surface again and again—often buried under too much data and too little insight.

That’s why I developed SLI_Insight, a local expert system that mirrors the way I think, work, and solve problems. It’s not just a chatbot. It’s a distilled version of my consulting methodology—integrating decades of technical experience with a structured database of real failure reports, backed by deep AI summarization.

This tool makes my expertise more accessible and more powerful for clients who need real answers, fast.

⸻

What SLI_Insight Does

SLI_Insight is a locally run expert assistant that helps identify failure causes, trace technical patterns, and retrieve key findings from thousands of archived failure analysis reports. It doesn’t rely on cloud APIs or black-box services. Everything stays local, secure, and private.

The system:

✅ Accepts natural-language queries like:

“What causes solder joint fractures on ENIG plated boards?”

✅ Instantly matches those queries to real report tags using a custom keyword index

✅ Uses SQLite to retrieve relevant sections (background, results, conclusions, figures) from prior reports

✅ Uses a local LLaMA 3.2 model to summarize the findings—grounded in real casework

✅ Outputs a clean, timestamped markdown log of the session and final summary

⸻

How I Built It

The core components of SLI_Insight reflect how I approach every consulting problem:

🧠 Knowledge-Driven Search

The system uses pre-tagged keywords and job classification data, drawn from thousands of real SEM Lab reports. Instead of relying on vague AI guesses, it retrieves failure analysis content that matches the exact technical terms you care about—cracks, CAF, ENIG corrosion, MLCC knit line failure, and more.

🧰 Structured Retrieval + SQL Logic

Each match triggers SQL queries that pull:

•The original background, results, and conclusions

•Any figure captions and image filenames

•Keywords used in the report

This structured access means I can link a symptom (e.g. “thermal fatigue”) to dozens of real-world case examples in seconds.

🤖 Local Summarization with LLaMA

At the end of each session, SLI_Insight sends relevant text into a locally running LLaMA 3.2 model for expert summarization. Unlike chatbots that “guess” answers, this summary is grounded in actual case data—something no public model can offer.

📝 Everything is Logged and Exported

All interactions are stored in a markdown file, making it easy to build reports, client updates, or technical writeups from any session. The assistant also auto-saves a standalone summary of each session’s key findings.

⸻

Why This Matters for Clients

SLI_Insight isn’t just a clever toy. It’s a force multiplier for my consulting services:

•I can find precedents and patterns in seconds, not hours

•I can trace uncommon failures back to materials, processes, or conditions

•I can deliver findings backed by data—not hunches

In short, I can help your engineering team solve problems faster, with clearer documentation and higher confidence in root cause.

⸻

Interested in Working Together?

If you’re facing yield loss, intermittent failures, or unexplained component damage—and you don’t have months to spare—I can help.

You bring the symptoms and the samples.

I bring the method, the memory, and the insight.

👉 Reach out to start a conversation.

ehare@semlab.com

SEM Lab, Inc.

 

 

Drilled Hole Roughness (Ra) as a Metric for PWB Reliability

Ed Hare, PhD – SEM Lab, Inc.

Drilled hole quality is often overlooked as a contributing factor to long-term reliability in printed wiring boards (PWBs). In particular, surface roughness of the drilled hole wall, commonly reported as Ra (arithmetic average roughness) or Rq (root-mean-square roughness), can have a significant impact on performance and failure risk.

⸻

Why Rough Drilled Holes Matter

Fabrication Indicator
Poorly drilled holes are often a fabrication quality issue—commonly related to drill bit wear, improper feed/speed, or inadequate desmear. Excessively rough drilled hole interiors are indicative of poor process control during board fabrication.

CAF Failures
Rough hole walls can create micro-crevices that promote conductive anodic filament (CAF) formation under applied bias and elevated humidity. These sites serve as initiation points for copper migration, especially in high-density multilayer designs.

Electrical Noise
Non-uniform copper topography inside the via barrel may also contribute to electrical performance variation in high-speed or RF applications. These effects are often masked during initial testing but become problematic under long-term use.

Stress Risers
Jagged or mechanically damaged areas along the drilled wall act as stress risers, which can limit fatigue life under thermal or mechanical cycling. This often results in copper barrel cracking or interconnect failure over time.

⸻

Measurement and Analysis

At SEM Lab, we use high-resolution SEM imaging and software-based analysis to calculate Ra and Rq from drilled hole interiors. Measurements are obtained from multiple regions of interest within the via structure, and plotted against PWB lot, drill column, or via position.

This approach allows for identification of outliers caused by tool wear or board stack variation. Regions with elevated Ra values may correlate with plated copper pull-away or localized delamination when subjected to thermal cycling.

⸻

🔧 Recommendations
• Evaluate Ra and Rq from representative drilled holes on each new PWB lot.
• Use SEM or profilometry tools—optical inspection is insufficient for identifying roughness-based failure risk.
• Set internal benchmarks (e.g., Ra < 2.0 µm) for critical layers and high-reliability applications.
• Include drilled hole roughness as a QA parameter when auditing new board suppliers.

⸻

Support Available

SEM Lab Inc. now offers remote consulting services to support engineers involved in resolving product quality issues. If you’re encountering via-related failures or want to strengthen your board qualification process, I can assist by reviewing failure data and providing recommendations based on decades of laboratory experience.

📧 ehare@semlab.com
🌐 www.semlab.com

PWB Internal Short – Example C

This slide presents a failure analysis case study of a printed wiring board (PWB) that developed an internal short during burn-in testing. The cross-sectional SEM images highlight localized laminated damage, which was likely caused when a warped board was forcibly mounted flat, inducing internal mechanical stress. Comparison with an undamaged region confirms the localized nature of the failure. Additionally, the use of an unusual blind via construction appears to have exacerbated the issue, contributing to the internal short.

 

 

Investigating Internal Shorts in PWBs: Example B

In multilayer printed wiring boards (PWBs), internal shorts can arise from subtle but critical manufacturing defects. This case study highlights a failure mode linked to drill or inner layer misregistration, which compromised the electrical clearance between a plated through-hole (PTH) via and a 24V internal plane. The resulting drill-induced laminate damage, combined with radial cracking, facilitated an unintended electrical bridge. Through microsectional and optical analysis, we demonstrate how mechanical misalignments propagate into latent electrical reliability risks.

 

 

 

Power and ground plane shorts in multilayer PCBs can be difficult to trace, especially when the root cause lies deep within the laminate structure. This example highlights an internal short caused by resin fracture and delamination, which enabled copper electro-migration across a thin dielectric layer. Understanding failure mechanisms like this is essential for improving PCB reliability in demanding applications. #FailureAnalysis #PCBDesign #ElectroMigration #MaterialsScience