Thin Film Thickness Measurements Using EDS


SEM Lab, Inc. has developed a method for measuring thickness of thin film deposits on various substrates, including multiple layers of different materials, using EDS data.  The method is extremely efficient and is therefore a cost effect alternative to conventional and FIB microsection techniques (approximately half the cost).

One application for this method is measurement of aluminum deposits on silicon die, particularly wire bond pads. The example below (Fig. A) shows a BSE SEM image and raster scan EDS spectrum of an aluminum bond pad on silicon, and the calculated thickness of the aluminum layer.

A second example (Fig. B) is gold plating thickness over nickel or nickel-phosphorus alloy.  The thickness of the gold layer can be determined for electroless-nickel immersion-gold (ENIG) PWB finishes and thin electro-plated gold (< 15 microns) on boards or component leads.

There are numerous other applications for this measurement method, which has significant advantages over conventional direct measurements on cross-sections including,

  • Measurement requires only one EDS spectrum versus multiple direct measurements from cross-sections to achieve a meaningful average
  • Non-destructive to the location being examined
  • Simultaneous acquisition of image to document surface morphology
  • Approximately half the cost of conventional and FIB microsection techniques

In summary, SEM Lab, Inc. can provide thickness measurements of thin film deposits on various substrates, including multiple layers of different materials, using EDS data for approximately half the cost of conventional and FIB microsection techniques.  Please contact us to discuss your specific requirements for measurements of thin film deposit thickness.

BSE SEM image and raster scan EDS spectrum of aluminum bond pad on silicon.

Fig A – BSE SEM image and raster scan EDS spectrum of aluminum bond pad on silicon.



Gold over nickel-phosphorus alloy on flex connector contact fingers

Fig B – Gold over nickel-phosphorus alloy on flex connector contact fingers.


EOS damage on this chemically decapsulated operational amplifier was more subtle than most cases that we have analyzed. This suggests that the stress condition was likely just above the maximum operating conditions for the device. In this case the damage was associated with an output pin likely overloaded by another device.

Other examples of EOS damage can be found here …

Example 1  Example 2


BGA Assembly Verification

SEM Lab, Inc. provides a comprehensive approach to BGA assembly validation using microsection and SEM analysis.  The results can be used to optimize assembly processes early in the product development cycle and help to prevent failure during production. [see presentation]

BGA warpage - How much is too much?
Calculating warpage based on measurements from BGA microsections.



SEM Lab, Inc. has seen a number of knit line related failures in multilayer ceramic capacitors since 2002 when three different cases appeared (i.e. different clients & different MLCC manufacturers). Here are some examples of what this defect looks like …

August 2002

August 2002

February 2008

July 2009

August 2019

September 2019

A plot of the cumulative analysis tasks performed by SEM Lab, Inc. that involved knit line related failures is shown below. It is not clear if the up tick in these occurrences is real or not because of the limited data set. However, this may be something to be concerned with because this can be considered a latent defect that is rather difficult to screen out.  This condition does not significantly affect electrical parameters of the capacitors and is not typically visible in non-destructive techniques such as x-ray imaging.  The knit line fractures tend to cause damage in the adjoining dielectric layers and often cause secondary fracture in the dielectric between opposing electrodes resulting eventually in internal short circuits.

Knit line fractures are considered a capacitor manufacturing defect caused by lamination problems such as poor adhesion between the metal and dielectric layers.  As such, it should be routinely monitored using microsection analysis on a suitable sample of each production lot of capacitors.  However, the rate of occurrence may be too small to be detected in lot samples.  That might explain why we continue to see knit line fractures in our laboratory.


A client provided a failed CMOS Flip-Flop IC to SEM Lab, Inc. for failure analysis.  An output signal reportedly failed when the circuit was connected to an electronic counter.

This is a BSE SEM image of the device after grinding through the alumina ceramic top of the CerDip package into the die cavity. The bond wires on the device were found to be intact.

SEM examination of the die area associated with the output signal revealed that the metal run between the wire bond pad and the first contact on the die was fused open.

This is a higher magnification image of the metal run between the wire bond pad and the contact that fused open.

The dimensions of the fused section of metallization and the bond wire were estimated and input into a model for calculation of the electrical overstress (EOS) event pulse width.  The pulse width was estimated as in the range of 1-100 microseconds, which is consistent with a high voltage transient EOS event.

This image shows the same output area on a known good device for comparison.

The analysis results suggested that the electronic counter associated with the failure should be investigated for proper grounding.


SEM Lab, Inc. supports printed wiring board failure analysis and construction analysis.  This presentation documents some of the most common failure causes seen in this laboratory.  These include Hi-Pot failures, lamination failures, inner layer separation, corrosion failures, PTH Cu-plating failures, and conductive anodic filament failures.  These failures can be mitigated to a significant degree by utilizing construction analysis to verify PWB quality.  Construction analysis allows assessment of conductor layer thickness, dielectric layer thickness, PTH copper thickness, layer-to-layer registration, standard via & micro-via quality, PTH fill quality, and drilled-hole quality to name a few critical feature attributes. Download >>>  Failure Analysis of PWBs

These are some representative examples of corrosion failure of electronic components and assemblies characterized in this laboratory.

Example 1: This is a BSE SEM image of a contact tine from a telecommunications jack. The tine is gold-plated over a nickel-underplate over copper alloy. The primary corrosion product was copper oxide that indicated corrosion of the tine base metal. Corrosive agents were found on the surface including sodium and potassium hydroxides, which in the presence of moisture can result in galvanic attack of the base metal through minute defects (pores and seams) in the plating resulting in the type of damage observed here.

Example 2: This is an electro-mechanical relay that failed to function due to internal corrosion where the corrosion product (rust) prevented the armature from fully actuating. Bromine was found in the corrosion product, which likely accelerated the corrosion damage.

Example 3: This is an example of severely corroded PTH-vias as viewed from the PWB surface and in cross-section. The corrosion appears to have been caused by residual chloride from a highly activated soldering flux. The un-filled vias easily trap process chemicals including solder flux. Another example of a corroded PTH-via is shown here.

Example 4: This is an aluminum bond pad on a failed plastic-molded op amp that was chemically decapsulated. The aluminum bond pad had been nearly completely etched away due to internal corrosion, which resulted in failures due to increased electrical resistance. Some aluminum remained in the corners of the pad (arrows). CSAM imaging showed internal separation of the molding compound from the die surface and lead frame. In addition, fractures were found in the plastic molding compound suggesting that the parts were damaged by “popcorning” during solder reflow.

Corrosion related electronics failures are common in this laboratory’s experience.

These are some representative solder joint failure modes found in this laboratory that illustrate

* mechanical overload at high strain rate,
* thermal fatigue accelerated by gold embrittlement,
* creep rupture failure

Example 1: This is an SMT thick film resistor solder joint. The solder joint failed in a brittle fracture mode at the interface between the solder and the nickel barrier plating (i.e. brittle interfacial fracture). The analysis results suggested that the resistor failure was most likely caused by mechanical stress (likely in bending) at a high strain rate.

Example 2: This example shows a thermal fatigue fracture. The solder alloy is SN63, the package is a J-lead PMIC, and it is soldered to an alumina substrate. The thermal fatigue fracture showed classic characteristics such as grain boundary separation and propagation through the bulk solder joint. In this case, the failure was accelerated by gold embrittlement of the solder joint (bulk solder joint contained ~ 3 wt% of gold). Fracture is driven by cyclic creep-fatigue damage due to elastic displacement of the leads being converted to time-dependent plastic (creep) strain in the solder joint during thermal cycling. The cyclic strain is due to CTE mismatch between the PMIC and the ceramic substrate.

Example 3: This example shows a creep rupture failure of an SMT connector solder joint. The lead that failed was under stress as-soldered. The vertical displacement of the lead after the solder joint fractured is the key feature that suggests this was a creep rupture failure. The elastic strain of the lead is converted to creep strain in the solder joint until it either ruptures or the stress is relieved.

It is important to identify the failure mode accurately in order to formulate appropriate corrective actions.