LEDs fail for a variety of reasons ….
Vias are important features in printed circuit boards as they distribute signals from one layer to another. Occasionally, faulty vias are responsible for electrical failure of PCBAs. This post illustrates a variety of printed wiring board vias and some of the defect conditions we have observed that are associated with vias.
These are thermal PTH-vias associated with a QFN device. The vias are intended to be solder filled, but the solder is nearly absent on one of these two vias, which defeats the purpose of heat conduction away from the device.
This is a polymer filled PTH-via that exhibited a plating problem. The printed circuit board is a QFN device substrate, where an open circuit condition was attributed to the defective plating.
This is a high aspect ratio polymer filled and capped PTH-via that exhibited excellent fill density and copper thickness in the hole.
This is a high aspect ratio polymer filled and capped PTH-via that exhibited excellent fill density but showed insufficient copper thickness in the central region of the holes.
This is a high aspect ratio polymer filled and capped PTH-via that exhibited excellent fill density and copper thickness in the hole (left). However, there was a weakness associated with copper adhesion of the cap to the plated edge of the hole that cause open circuits post reflow soldering (right).
More examples can be found here:
Flux Cleaning is Essential
PCBA cleaning (called flux cleaning or defluxing) is extremely effective in solving or preventing problems caused by flux residue.
Use of high-density mounting of components on PCBAs is accelerating, and in these cases even a small amount of flux residue may cause electrical isolation losses affecting signal integrity. In these cases, flux cleaning is required.
Cleaning, specifically flux cleaning or defluxing, is highly effective in addressing and preventing issues caused by flux residue. Flux residue can lead to various problems such as increased electrical conductivity on the board surface, increased risk of corrosion, and compromised reliability of electronic components.
When low-residue or no-clean flux is used, there are cases where the flux cleaning process is omitted. However, in fields where high reliability is required, such as automotive modules and space-related equipment, the flux residue cleaning process is essential to avoid the problems described above.
Ionic cleanliness refers to the measure of ionic contamination present on the surface of a material or component, typically in the field of electronics manufacturing. It quantifies the amount of electrically conductive ions, such as chloride, sulfate, and other residues, that are left behind after manufacturing processes like soldering, flux application, or cleaning.
Ionic contamination can occur due to various factors, including the use of fluxes, soldering materials, handling processes, and environmental conditions. These ionic residues, if not properly controlled or removed, can have detrimental effects on the reliability and performance of electronic devices.
To assess ionic cleanliness, a common method is to measure the electrical conductivity of an extracted solution from the material or component. This is typically done using techniques like ion chromatography (IC) or resistivity of solvent extract (ROSE) testing. The results are expressed as the concentration of ionic species, typically in units of parts per million (ppm) or micrograms per square centimeter (μg/cm²).
Standards such as the IPC-TM-650 and MIL-STD-2000 provide guidelines and specifications for acceptable levels of ionic contamination in different electronic assemblies or components. These standards help manufacturers ensure that the ionic cleanliness requirements are met to maintain the reliability and functionality of the final products.
Overall, the goal is to ensure optimal performance, reliability, and longevity of electronic devices by addressing flux residue, maintaining adequate ionic cleanliness levels, and mitigating the impact of moisture. Adhering to industry standards and manufacturer guidelines is essential in implementing effective cleaning processes to meet the specific requirements of different applications and sectors.
Introduction
Our failure analysis laboratory has seen several cases of the same WLED failure mechanism in the past two years, where the lens material is Ce:YAG phosphor in silicone elastomer and the failures appear to be caused by degradation of the lens material. This paper uses three cases to illustrate this failure mechanism and the failure modes associated with it.
The WLED technology for these cases utilize cerium-doped yttrium alumina garnet (Ce:YAG ) phosphor particles suspended in optically clear silicone elastomer. This material appears to be yellow in color because the phosphor particles convert blue light to yellow light. The phosphor-converted WLED is viable because the combination of blue and yellow appears to the eye as white light.
Ref. [1] states that “The unique silicone polymer utilized in pc-LEDs is stable over a wide temperature range and resistant to yellowing after ultraviolet exposure.” If this is the case, then the failures discussed below were likely caused by some sort of abuse, which is likely related to the intensity of white light being generated by the LEDs or the quality of the thermal designs associated with these applications. The cases discussed below involved very bright LEDs and the thermal designs appeared to be quite good.
Case Histories
Case #1: COB WLEDs
Case #1 is related to a chip-on-board (COB) WLED that reportedly failed within approximately half of its expected life due to color shift toward blue light. EDS analysis (Fig. 1A) suggested that the failure mechanism involved carbon loss. FTIR analysis (Fig. 1B) of the silicone coating from the “New” sample suggested that the silicone is polymethylphenylsiloxane. Furthermore, comparison of the FTIR spectra for “New” and “Fail” samples (Fig. 1C) suggested that the degraded silicone coating on the failed LEDs correlates with the disappearance/weakening of Si-Ph absorption peaks, which implies that the phenyl rings in the compound disappear during the degradation process. This mechanism may explain the loss of carbon in the silicone material shown by the EDS data.
Fig. 1A – EDS results for “New”, “Not-Yet-Failed”, and “Failed” WLEDs (atomic percent) where “(n%)” indicates the estimated amount of life consumed for each condition
Fig. 1B – FTIR spectrum of the silicone coating from the “New” sample (top) along with the best match from our spectral library (bottom).
Fig. 1C – FTIR spectra of the failed (top) and control (bottom) samples.
The loss of carbon in the silicone appears to cause shrinkage and fracture in the coating (Fig. 1D). The fractures provide a path for blue light to escape without phosphor conversion, which might explain the color shift toward blue that was reported as the failure mode.
Fig. 1D – SEM micrograph of Ce:YAG-silicone coating. Bright contrast particles are Ce:YAG phosphor. Intermediate gray contrast material is silicone elastomer. Dark contrast features are fractures in the silicone elastomer.
Case #2: Packaged WLED
Case #2 is a conventionally packaged WLED that, like case #1, failed within approximately half of its expected life. However, in this case the failure mode was catastrophic with evidence of gross electrical overstress damage. Fig. 2A shows a WLED that remained functional, but showed damage to the Ce:YAG-silicone lens including deep fractures in the silicone that exposed the LED die to the environment. The operating environment in this case was corrosive, and the combination of the fractures in the silicone lens and the corrosive environment led to catastrophic failure as shown in Fig. 2B.
Fig. 2A – WLED that was still functional, but shows damage to the Ce:YAG-silicone lens.
Fig. 2B – WLED that failed catastrophically.
EDS data for the Ce:YAG-silicone lens material for Case #2 showed 50 ± 11 atomic percent carbon (N = 18) compared with 42 ± 6 atomic percent carbon (N=6) for Case #1, which indicates that the silicone material was less degraded on average for Case #2 than for Case #1. This is believed to be because light intensity in the silicone is uniform for Case #1 and varies as a function of location for Case #2. For Case #2, the light intensity is highest directly over the LED die and lower near the periphery of the lens. Since the EDS data was from random locations within the lens for Case #2, the average is skewed to higher atomic percent carbon due to material that was near the periphery of the lens that was not subjected to full light intensity (e.g. Case #3).
Case #3: Packaged WLED2
This case is another packaged LED as shown in Fig. 3A. The failure mode in this case was open circuits caused by failure of either the bond wires or the wire bonds depending on the sample. The lens material is the same type of Ce:YAG-silicone as the previous cases. In this case, EDS data showed 58 ± 10 atomic percent carbon (N = 6) at random locations within the lens material. This was the highest carbon percentage for failed LEDs of the three cases, and for the same reasons discussed in Case #2 it is believed that the average is skewed to higher atomic percent carbon due to nonuniformity of light intensity in the lens material.
Fig. 3A – LED showing two fractures in lens centered on each of two LED dice.
Fig. 3B shows EDS data for the Ce:YAG-silicone lens material of new LEDs and two failed LEDs. The data suggests that there is a loss of carbon for the failed LEDs relative to the new LEDs. Fig. 3C shows a mapping of carbon concentration in the silicone lens material versus location, which demonstrates that the degradation is most severe directly over the LED die where the fractures formed in the lens.
Fig. 3B – EDS data for composition of Ce:YAG-silicone lens of new LEDs and two failed LEDs.
Fig. 3C – Atomic percent carbon versus location relative to the die region of the LED.
Summary
The three cases illustrated above exhibited different failure modes, but they all appear to be caused by the same failure mechanism. This mechanism is characterized by …
- Shrinkage and fracture of the Ce:YAG-silicone lens or coating
- Loss of carbon due to outgassing of VOCs (phenyl groups)
- Unexpected early wearout failure
[1] Pradeep Lall, Hao Zhang, & Lynn Davis, “Failure Mechanisms and Color Stability in Light-Emitting Diodes during Operation in High- Temperature Environments in Presence of Contamination”, 2015 Electronic Components & Technology Conference, 1624 – 1632.
SEM Lab, Inc. uses SEM/EDS analysis to characterize ENIG finish quality on PWBs, as discussed here and here. Examples of gold thickness values obtained in this laboratory (N = 14) are illustrated in the histogram shown below. IPC-4552 suggests that the range of acceptable thickness is 0.0508 – 0.2032 microns, so 6 of the measurements exceeded the expected thickness. This may be the case because some suppliers provided thin electro-plated gold in place of immersion-gold when the finish was specified as ENIG.
The phosphorus concentration in the electroless-nickel is expected to be 7 – 9 wt%, which corresponds with “medium phosphorus” electroless-nickel. We detected one value below 7 wt% P, which can lead to corrosion of the electroless-nickel deposit during the immersion-gold plating process. Values above 9 wt% P can lead to solderability issues during the assembly process.
Routine measurements of gold thickness and phosphorus concentration in electroless-nickel on incoming board lots is an important way to avoid costly processing problems at assembly and reliability issues in the field. SEM Lab, Inc. has developed a cost effective approach to evaluating ENIG quality on PWBs.
SEM Lab, Inc. performed failure analysis on a diode bridge. Electrical tests results suggested that one of four internal diodes had short circuited.
The module was chemically decapsulated and the shorted die was isolated for SEM/EDS analysis. This is a BSE SEM image of the shorted die.
The suspected short site was located near a corner of the die.
An elemental map confirms that the suspected short is a silicon melt pipe.
Higher magnification images of the site also confirmed it is the breakdown site.
The size of the breakdown site is related to the melt-thru current [1], which in this case is estimated as ~14.3 amperes. The location of the melt through suggests that the breakdown was caused by a high voltage transient.
[1] J. T. May, “Limiting Phenomena in Power Transistors and the Interpretation of EOS Damage”, in Microelectronics Failure Analysis Desk Reference, 3rd Edition, ASM International Press, 1993, pp. 321-328.
SEM Lab, Inc. created a video (link below) to illustrate simulation of BGA solder joints during the reflow solder process. This approach allows us to determine at what height the solder joint becomes unstable and separates into two droplets during reflow. This simulation tool will be useful for identifying the BGA warpage value that would be expected to cause defects such as head-in-pillow.
QFN failures are increasingly important as more devices are offered in this package style, sometimes exclusively. There are some notable manufacturing issues related to assembly processes for QFNs, and this post discusses two of the more common ones that cause failures.
Trapped conductive residue under the device
The capillary gap under assembled QFNs is typically very small and difficult to clean, so solder flux residue and moisture lead to corrosion and electrical leakage causing what initially looks like a device failure. The example below shows this type of condition and resulted in failure.
Another example shows several QFN signals bridged by conductive residue.
CCE mismatch induced warpage and subsequent failure of solder joints
The QFN package typically contains a relatively large volume fraction of silicon relative to other package styles, which creates a significant CTE mismatch between the QFN and the board. In addition, the solder joint height is minimal resulting in increased stiffness of the solder joints. These factors can lead to substantial residual stress in the solder joints. Any additional mechanical stress due to depaneling or ICT probes can overload the solder joints resulting in fractures. The example below shows a fractured joint that popped up indicating there was residual elastic strain in the QFN and PWB after assembly.
The examples of manufacturing issues related to assembly processes for QFNs discussed above suggest a need for rigorous process validation for both solder reflow and cleaning processes.
Quality problems identified during failure analysis performed by SEM Lab, Inc. over the past couple of decades.
Example 1
This is an example of bad HASL finish, likely due to inappropriate air knife pressure. The problem caused inadequate solder coverage of the component mounting pads, which resulted in exposed Cu-Sn IMC and caused a severe solderability problem during assembly of the PWAs.
Example 2
This example shows delamination of an internal layer. The delamination likely occurred as a result of a contaminant trapped at the interface between the B-stage and the copper-clad laminate during PWB lay-up.
Example 3
This example shows the condition referred to as resin recession, where resin recedes from the copper barrel after cooling from a thermal excursion.
Example 4
This is an example of poor drilled hole quality and thin (< 1-mil) copper plating of the hole walls.
Example 5
This is an example of a very high aspect ratio PTH-via on a high layer count board. The quality is very good considering the difficulty of fabricating high aspect ratio PTH-vias.
Example 6
This example shows poor drilled hole quality and resulting laminate damage including a substantial crack with copper plating extending well past the outside diameter of the PTH.
Example 7
This example shows gross damage after a conductive anodic filament shorted adjacent signals, +12V and GND at a through-hole connector.
Example 8
These are neighboring holes for the previous example that had not been damaged, which showed poor drilled hole quality, laminate damage, and copper plating extending well across the isolation space between PTHs.
Example 9
This is an example of inner layer separation from the PTH wall, which is most like due to resin smear and inadequate de-smearing prior to copper plating. This could have passed electrical testing as there is enough connection that it might not have been detected.
Example 10
This is another example of inner layer separation, which was likely exacerbated by a thermal excursion.
Example 11
This example shows a PTH-via with thin plating between two Vias with nominal plating thickness. There were plating nodules near the top and bottom of the hole that likely restricted access of the plating solution to the central region of the hole.
Example 12
This is a BGA assembly where the PTH-via on the right corroded open, which was due to poor via-fill allowing corrosive solder flux to become trapped in the hole.
Example 13
This PWB is an LED substrate with an over-molded body. The PTH copper shows and example of “skip plating” where no copper deposited on the hole wall. There is also thin plating on the opposite side. Together these resulted in an open circuit condition.
Example 14
This is an example of inadequate copper plating thickness in a PTH.
Example 15
This examples shows a circumferential barrel crack in the center of the PTH, which is likely due to a combination of excessive Z-axis expansion and perhaps poor copper ductility.
Example 16
This is an optical image of a micro-sectioned PWB using dark field imaging. The reflections of groups of glass fibers intersecting with the hole is an indication of laminate damage due to drilling, which can reduce CAF resistance.
Example 17
This is an example of a copper plating nodule on the ID of a PTH.
Example 18
This image shows delamination of epoxy resin from fiber bundles as well as resin starvation. It is likely that the resin starvation condition caused excessive moisture entrapment and subsequent popcorn damage when the moisture vaporized at elevated temperature (e.g. lamination or solder reflow).
SEM Lab, Inc. recently announced a new capability for measurement of thin film layer thickness using EDS data. This post shows an example where the aluminum bond pad thickness and the underlying Ti-W barrier metal layer thickness are measured simultaneously on a silicon IC device. Fig. A shows the EDS spectra of three bond pads on the device. Fig. B shows the layer thickness values for two different devices (A & B) at three different bond pads (1, 2, & 3).
Fig. A – EDS spectra of three bond pads on a device die.
Fig. B – Layer thickness values for two different devices (A & B) at three different bond pads (1, 2, & 3).
The ability to measure the aluminum bond pad thickness and the underlying Ti-W barrier metal layer thickness simultaneously makes this a very efficient method for characterizing IC devices.